//-----------------------------------------------------------------------
// Question 2 - Elec 3720 - Ethan Holt 3144462 - 5 Word 1Hz Rotate
//-----------------------------------------------------------------------
module question2(input CLOCK_50, output [6:0]HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0);

wire [2:0] M7,M6,M5,M4,M3,M2,M1,M0;
reg [2:0]OUT;
parameter H =0,E=1,L=2,O=3,blank=4;

Onehz Delay(CLOCK_50, onehertz);

Mux8to1  m7(OUT,blank,blank,blank,H,E,L,L,O,M7);
Mux8to1  m6(OUT,blank,blank,H,E,L,L,O,blank,M6);
Mux8to1  m5(OUT,blank,H,E,L,L,O,blank,blank,M5);
Mux8to1  m4(OUT,H,E,L,L,O,blank,blank,blank,M4);
Mux8to1  m3(OUT,E,L,L,O,blank,blank,blank,H,M3);
Mux8to1  m2(OUT,L,L,O,blank,blank,blank,H,E,M2);
Mux8to1  m1(OUT,L,O,blank,blank,blank,H,E,L,M1);
Mux8to1  m0(OUT,O,blank,blank,blank,H,E,L,L,M0);

SSD_Decoder   Disp7(M7, HEX7);
SSD_Decoder   Disp6(M6, HEX6);
SSD_Decoder   Disp5(M5, HEX5);
SSD_Decoder   Disp4(M4, HEX4);
SSD_Decoder   Disp3(M3, HEX3);
SSD_Decoder   Disp2(M2, HEX2);
SSD_Decoder   Disp1(M1, HEX1);
SSD_Decoder   Disp0(M0, HEX0);

always @(posedge onehertz)
	begin
		if (OUT!=7) OUT = OUT+1; else OUT=0;
	end			

endmodule
//----------------------------------------------------------
// implements a 3-bit wide 8-to-1 multiplexer
module Mux8to1(input [2:0] S, T, U, V, W, X, Y,Z,A, output reg[2:0]M);

	always @ (*)
		case (S)
			0 : M = T;  
			1 : M = U; 
			2 : M = V;
			3 : M = W;
			4 : M = X;
			5 : M = Y;
			6 : M = Z;
			default : M = A;
		endcase
		
endmodule
//---------------------------------------------------------
// implements a 7-segment decoder for H, E, L, O, and ‘blank’
//---------------------------------------------------------
module SSD_Decoder (input [2:0] State,output reg [6:0] HEX);
	always @ (*)
		case (State)
			0 : HEX = 7'b0001001;  //H
			1 : HEX = 7'b0000110; //E
			2 : HEX = 7'b1000111; // L
			3 : HEX = 7'b1000000; // O
			default : HEX = 7'b1111111;
		endcase

endmodule
//-------------------------------------------------------------
//implements 1Hz clock from 50Mhz board clock
//-------------------------------------------------------------
module Onehz (input clk, output reg onehertz);          
  reg[25:0] count = 0;
  
  always @ (posedge clk) begin
    onehertz <= (count == 50000000 - 2);
    count <= onehertz ? 0 : count + 1;
  end
endmodule