library ieee;
use ieee.std_logic_1164.all;
entity Controller2 is
port
	(
		Q1, Q0, IR2, IR1, IR0: in std_logic;
		D1, D0, MSA1, MSA0, MSB1, MSB0, MSC2, MSC1, MSC0, IncPC, IRLD, PCLD: out std_logic
	);
end Controller2;

architecture logic of Controller2 is

signal EV : std_logic;

begin

	D1 <= ((not Q1) and Q0 and (not IR2) and (not IR1) and IR0) or
		((not Q1) and Q0 and IR2 and (not IR1) and IR0);

	D0 <= ((not Q1) and (not Q0)) or
		((not Q1) and Q0 and IR2 and (not IR1) and IR0);

	MSA1 <= ((not Q1) and Q0 and (not IR2) and IR1 and (not IR0)) or
		((not Q1) and Q0 and (not IR2) and IR1 and IR0) or
		((not Q1) and Q0 and IR2 and (not IR1) and (not IR0));

	MSA0 <= ((not Q1) or Q0);

	MSB1 <= (Q1 or (not Q0) or IR2 or IR1 or IR0);

	MSB0 <= ((not Q1) and Q0 and (not IR2) and (not IR1) and (not IR0));

	MSC2 <= ((not Q1) and Q0 and (not IR2) and IR1 and (not IR0)) or
		((not Q1) and Q0 and (not IR2) and IR1 and IR0) or
		((not Q1) and Q0 and IR2 and (not IR1) and (not IR0));

	MSC1 <= ((not Q1) and Q0 and (not IR2) and IR1 and (not IR0)) or
		((not Q1) and Q0 and IR2 and (not IR1) and (not IR0));

	MSC0 <= ((not Q1) and Q0 and (not IR2) and IR1 and (not IR0)) or
		((not Q1) and Q0 and (not IR2) and IR1 and IR0);

	IncPC <= ((not Q1) and Q0) or
		(Q1 and (not Q0));

	IRLD <= ((not Q1) and (not Q0));

	PCLD <= (Q1 and Q0);
	

end logic;