library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity afsk_modulator is
port (
	clk: in std_logic;
	serial_in: in std_logic;
	audio_dac_out: out std_logic_vector(3 downto 0);
	test_mode: in std_logic;
	tx_active: out std_logic
);
end afsk_modulator;

architecture x of afsk_modulator is
	type sin_rom_type is array(0 to 15) of std_logic_vector(3 downto 0);
	constant sin_map: sin_rom_type := (
		x"8", x"b", x"d", x"e", x"f", x"e", x"d", x"a",
		x"7", x"4", x"2", x"1", x"0", x"1", x"2", x"5"
	);
	signal a,b,suma:std_logic_vector(31 downto 0);
	signal R_tx_acc: std_logic_vector(31 downto 0);
	constant c1: std_logic_vector(31 downto 0) := conv_std_logic_vector(206158,32); --1200 Hz
	constant c0: std_logic_vector(31 downto 0) := conv_std_logic_vector(377957,32); --2200 Hz
	signal send: std_logic;
	
begin
	tx_active <= send when test_mode = '0' else '1';
	
	process(clk)
		variable pause: std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
	begin
		if rising_edge(clk) then
			
			if serial_in = '0' then
				R_tx_acc <= R_tx_acc + c0;
			else
				R_tx_acc <= R_tx_acc + c1;
			end if;
			audio_dac_out <= sin_map(conv_integer(R_tx_acc(31 downto 28)));
			
			if send = '0' then
				if (serial_in = '0' or test_mode = '1') then
					send <= '1';
				end if;
			end if;
			
			if send = '1' then
				if serial_in = '0' then
					pause := conv_std_logic_vector(0,32);
				else
					pause := pause + '1';
					if pause = conv_std_logic_vector(50000000,32) then
						pause := conv_std_logic_vector(0,32);
						send <= '0';
					end if;
				end if;
			end if;
		end if;
	end process;
end;